Ques:- What is deffrence between switch & hub
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Ques:- Microsoft File and Print Sharing and Microsoft Domain clients don't work through IP Masq!
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Vantage Systech,
Ques:- Design a Transmission Gate based XOR. Now, how do you convert it to XNOR?
Asked In :-
Astra Microwave Products, Renesas Electronics, Skyworks Solutions, HELLA ELECTRONICS CORPORATION, honeywell, asml, panasonic, garmin international, daktronics, samsung semiconductor,
Right Answer:
To design a Transmission Gate based XOR, use two transmission gates (TG1 and TG2) and two inverters (INV1 and INV2). Connect the inputs A and B to the gates of the transmission gates as follows:
1. Connect A to the gate of TG1 and B to the gate of TG2.
2. Connect the output of TG1 to one input of INV1, and the output of TG2 to one input of INV2.
3. Connect the outputs of INV1 and INV2 together to get the XOR output.
To convert this XOR to XNOR, simply invert the output of the XOR. You can do this by adding an additional inverter (INV3) at the output of the XOR. The final output will be the output of INV3, which gives you the XNOR.
To design a Transmission Gate based XOR, use two transmission gates (TG1 and TG2) and two inverters (INV1 and INV2). Connect the inputs A and B to the gates of the transmission gates as follows:
1. Connect A to the gate of TG1 and B to the gate of TG2.
2. Connect the output of TG1 to one input of INV1, and the output of TG2 to one input of INV2.
3. Connect the outputs of INV1 and INV2 together to get the XOR output.
To convert this XOR to XNOR, simply invert the output of the XOR. You can do this by adding an additional inverter (INV3) at the output of the XOR. The final output will be the output of INV3, which gives you the XNOR.
Ques:- What is the Role of TCP/IP in data transmission from source to destination?
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b4b, modak analytics,
Ques:- What is NVT (Network Virtual Terminal)?
Ques:- How can we create VPN to connect to branch office of the same office.what would be the priliminary requirment?
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Ques:- Design any FSM in VHDL or Verilog.
Asked In :-
DIGICOMM Semiconductor, Medha Servo Drives, Mistral Solutions, Belden, EPIC Semiconductors, micron technology, lam research, microchip technology, xilinx, landis+gyr,
Right Answer:
```verilog
module fsm_example (
input clk,
input reset,
input in,
output reg out
);
typedef enum reg [1:0] {S0, S1, S2} state_t;
state_t state, next_state;
always @(posedge clk or posedge reset) begin
if (reset)
state <= S0;
else
state <= next_state;
end
always @(*) begin
case (state)
S0: begin
out = 0;
if (in)
next_state = S1;
else
next_state = S0;
end
S1: begin
out = 1;
if (in)
next_state = S2;
else
next_state = S0;
end
S2: begin
out = 0;
if (in)
next_state = S1
```verilog
module fsm_example (
input clk,
input reset,
input in,
output reg out
);
typedef enum reg [1:0] {S0, S1, S2} state_t;
state_t state, next_state;
always @(posedge clk or posedge reset) begin
if (reset)
state <= S0;
else
state <= next_state;
end
always @(*) begin
case (state)
S0: begin
out = 0;
if (in)
next_state = S1;
else
next_state = S0;
end
S1: begin
out = 1;
if (in)
next_state = S2;
else
next_state = S0;
end
S2: begin
out = 0;
if (in)
next_state = S1
Ques:- How do you detect a sequence of “1101” arriving serially from a signal line?
Asked In :-
Atigo Electronics India, Christie Digital, Astra Microwave Products, AdeptChip Services, Renesas Electronics, SignOff Semiconductors, E-T-A, honeywell, broadcom, amd,
Right Answer:
To detect the sequence "1101" arriving serially from a signal line, you can use a finite state machine (FSM) or a shift register. The FSM will have states corresponding to each bit of the sequence, transitioning through states as each bit is received. When the FSM reaches the final state after receiving "1101", it indicates that the sequence has been detected. Alternatively, a shift register can be used to store the last four bits received, and you can compare these bits to "1101" to detect the sequence.
To detect the sequence "1101" arriving serially from a signal line, you can use a finite state machine (FSM) or a shift register. The FSM will have states corresponding to each bit of the sequence, transitioning through states as each bit is received. When the FSM reaches the final state after receiving "1101", it indicates that the sequence has been detected. Alternatively, a shift register can be used to store the last four bits received, and you can compare these bits to "1101" to detect the sequence.
Ques:- How do you do authentication with message digest(MD5)? (Usually MD is used for finding tampering of data)
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Ques:- How can I measure the performance of an IP link?
Ques:- What?s a PCB?
Asked In :-
saankhya labs pvt. ltd., aura semiconductor,
Right Answer:
A PCB, or Printed Circuit Board, is a flat board made of insulating material that holds and connects electronic components using conductive pathways.
A PCB, or Printed Circuit Board, is a flat board made of insulating material that holds and connects electronic components using conductive pathways.
Ques:- What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?
Asked In :-
Atigo Electronics India, Circle Internet Financial, Vector India, American Megatrends Inc, American Megatrends India, Open-Silicon, AdeptChip Services, Cadmaxx Solutions, Team Robocon IITR, Dxcorr Hardware Technologies,
Right Answer:
Setup time is the minimum time before the clock edge that the data input must be stable, while hold time is the minimum time after the clock edge that the data input must remain stable. Setup time is critical for estimating the maximum clock frequency of a circuit.
Setup time is the minimum time before the clock edge that the data input must be stable, while hold time is the minimum time after the clock edge that the data input must remain stable. Setup time is critical for estimating the maximum clock frequency of a circuit.
